A quantitative model for quantum transport in nano-transistors

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U. Wulf1, M. Krahlisch1, J. Kucera2, H. Richter1, J. Hontschel3
1 BTU Cottbus-Senftenberg, Fakultat 1, Postfach 101 344, 3 013 Cottbus, Germany 2 Institute of Physics, Academy of Sciences of the Czech Republic,
Cukrovarnicka 10, 162 53 Praha 6, Czech Republic 3 GLOBALFOUNDRIES Dresden, Wilschdorfer LandstraSe 101,
1 109 Dresden, Germany wulf@physik. tu-cottbus. de, TheBrute@gmx. de, kucera@fzu. cz, richter@gfww. de, jan. hoentschel@globalfoundries. com
PACS 73. 23. A, 03. 65. Xp, 73. 63. -b
In a number of recent publications, a one-dimensional effective model for quantum transport in a nano-transistor was developed yielding qualitative agreement with the trace of an experimental transistor. To make possible a quantitative comparison, we introduce three phenomenological parameters in our model, the first one describing the overlap between the wave functions in the contacts and in the transistor channel, the second one is the transistor temperature, and the third one is the maximum height of the source-drain barrier. These parameters are adjusted to the traces of three experimental transistors. An accurate fit is obtained if the three adjustable parameters are determined for each gate voltage resulting in three calibration functions. In the threshold- and subthreshold regime the calibration functions are physically interpretable and allow one to extract key data from the transistors, such as their working temperature, their body factor, a linear combination of the flat band voltage and the built-in potential between substrate and source contact, and the quality of the wave function coupling between the contacts and the electron channel.
Keywords: nano-transistor, quantum transport, quantitative transistor model, nano-FET, drain current. 1. Introduction
The continuing reduction of the channel length for state-of-the-art nano-transistors necessitates a quantum mechanical treatment of carrier transport [1−3]. Here the solution of the Schrodinger equation can be achieved using a variety of methods. We choose the R-matrix formalism [4−13] to calculate the drain current of a planar MOSFET. In this approach it is possible to reduce in a systematic way a complete three-dimensional quantum-description of transport [6] to a one-dimensional effective model [7,10,11]. In this reduction process the assumption is made that only the lowest transverse mode in the electron channel contributes significantly to transport (single mode approximation, SMA). In Ref. [11], the SMA was shown to provide an accurate qualitative description of the drain current of an experimental nano-transistor. In this paper, our approach is extended to allow for a quantitative comparison with three further nano-transistors. To move from a qualitative to a quantitative description three suitable calibration parameters are introduced, one for the wave function overlap between the channel and the contacts, a second for the device temperature, and a third for the height of the source-drain barrier (calibrated SMA, cSMA). It is found that the cSMA allows an accurate fit for the ID — VD-traces of the experimental transistors if the three described parameters are determined for each gate voltage, resulting in three calibration functions. Even though the cSMA is a strongly simplified transistor model, a major advantage is that in the entire threshold- and subthreshold regime, all three calibration functions can be constructed in a simple and
physically interpretable way from four constants only (see dotted lines in Figs. 2 and 3). From the four fixed values of these constants, key data for the transistors can be extracted which take reasonable values.
2. Calibration of a one-dimensional effective transistor model
In the cSMA the drain current per width J is calculated according to:
J = CJ0 dt [s (t — m) — s (t — m + vD)] T (t). (1)
In addition to the multiplicative parameter C for the wave function overlap between electron channel and contacts, Eq. (1) is equivalent to the corresponding expression in the SMA [10, 11]: The normalization constant for the current per width is given by J0 = 2eN^hEF/(hX) where N? h is the number of equivalent conduction band minima in the electron channel, Ef is the Fermi energy in the source contact, X = h/V2m*EF is the scaling length, and m* is the effective electron mass. The current transmission T in Eq. (1) is calculated from the right-moving scattering solutions of the normalized Schrodinger equation
1 d2.. 1 + veff (x) — e

l2 dx2
^(x) = 0 (2)
which is the one-dimensional effective Schrodinger equation (3) in Ref. [10] with energies normalized to EF and lengths normalized to the channel length L = IX of the transistor. The normalized effective scattering potential is given by
(0 for x & lt- 0
Veff (x) = & lt- V0 — VDX for 0 & lt- X & lt- 1 (3)
[ - vD for X & gt- 1,
where VD = vDEF is the applied drain voltage and VO = v0EF is the maximum height of the source-drain barrier. (s. Fig. 1).
The effective potential is a Fowler-Nordheim-type field emission barrier used in the gate tunneling problem as well [15]. In the context of the transistor problem the simple trapezoidal form of the scattering potential corresponds to the neglect of image charges in the source-drain barrier associated with drain induced barrier lowering. In the effective potential veff the right-moving scattering states take the form ^?(x & lt- 0) = eikix + re-ikix in the source and ^(x & gt- 1) = te%k2x in the drain, with ki = VPe and k2 = l2(t + vD). The transmission coefficient t is calculated solving the discretized Eq. (2) by a recursive procedure and the current transmission is then given by T = k-i|t|2k2. The first factor of the integrand in (1) is the difference of the supply functions in the source- and in the drain contact calculated from
s (a) = a f^F-1 (-a), (4)
1 '- V 4n n uJ
where Fj is the Fermi-Dirac integral of order j = -½ and u = kBT/EF is the normalized temperature. The normalized chemical potential in the source contact is given by m = ^/Ef = uXi [4/(^v/nu3/2)], where Xi/2 is the inverse function of Fi/2. From Refs. [10] and [11] we adopt parameter values which are reasonable for a wide Si n-channel nano-FET with heavily doped contacts, X = 1 nm, J0 = 5×10−2A/^m, and EF = 0. 35eV.
Then, the channel lengths L =22 nm, 26 nm, and 30 nm of the three experimental transistors presented in the next section correspond to characteristic lengths of l =22, 26, and 30 and the chosen Fermi energy leads to u ~ 0.1 at room temperature.
Fig. 1. a) Field effect transistor (here conventional n-FET) with external circuitry. b) Normalized effective potential veff in Eq. (3) at different applied gate voltages. Solid lines: Quasi-OFF-state, v0 & gt- m, corresponding to Id — VD traces with positive curvature (s. filled rectangles in Fig. 2). Dashed lines: Threshold, v0 ~ m, the ID — VD trace exhibits a close-to-linear dependence on the drain voltage (s. asterisks in Fig. 2). Dotted line: ON-state corresponding to ID — VD traces with negative curvature (s. open circles in Fig. 2). Shown here is the effective potential for gate voltages slightly above threshold. For larger gate voltages, v0 increases above m because of device-heating (s. Fig. 3 (b)).
In the described one-dimensional effective model, neither the temperature, the barrier height nor the overlap parameter are known. To overcome this problem three calibration functions u (Vg), v0(VG), and C (VG) are introduced. These result from the minimization of the root mean square deviation
^¦Jrms (VG)

Jexp (Vh, Vg) — Jcal (VD, Vg)
J exp (Vd, Vg)
at given VG. Here Jexp (Vi, VG) is the experimental current measured at N equidistant drain voltages Vi where the calibrated theoretical current is calculated from (1) as
Jcal (Vi, Vg) = J (vd = V?/Ef, vo, u, C, l = L/X).
Fig. 2. In solid lines drain-characteristics Jexp of a series of n-channel nano-FETs with gate lengths of 22 nm ((A) linear scale and (B) logarithmic), 26 nm (© linear and (D) logarithmic), and 30 nm ((E) linear and (F) logarithmic). Marked with symbols Jcal according to Eq. (6): ON-state (open circles), experimental trace closest to the threshold trace at Vt (asteriks), and quasi-OFF-state (solid rectangles). In (B), (D), and (F) the dotted lines represent the four-constants-fit u = 0. 09, C = 0. 1, p = 2/V, v0 = -1V corresponding to the dotted lines in Fig. 3.
vG [V]
Fig. 3. Calibration functions (a) u (VG), (b) vo (VG), and © C (VG), filled circles L = 22 nm, symbols '-x'- L = 26 nm, and open rectangles L = 30 nm. In dotted lines the four-constants-fit u = 0. 09, C = 0. 1, 3 = 2/V, and v0 = -1V. The solid black line in (b) marks the position of m.
The function AJrms (VG) is then minimized by varying in (6) the parameters C, v0, and u. The parameter values leading to the minimum of AJrms (VG) constitute the calibration functions u (VG), v0(VG), and C (VG).
3. Results
The drain characteristics, Jexp, of a series of three nano-FETs with different channel lengths but otherwise equal nominal device structure are shown in Fig. 2. These traces are compared to the calibrated theoretical current per width Jcal (s. Eq. (6)), demonstrating a good agreement between theory and experiment. The calibration functions v0(VG), «(VG), and C (VG) obtained from the minimization procedure associated with Eq. (5) are plotted in Fig. 3. It can be determined that the calibration functions depend very little on the channel length. Furthermore, their gate-voltage-dependence shows two distinct regions separated by the threshold voltage VT ~ 0. 5V (arrows in Fig. 3). Here, VT follows from an inspection of the ID — VD-traces [11]: For gate voltages above VT, in the ON-state, the traces show a negative curvature, while below VT, it is positive. At VG = VT there is a close-to-linear threshold ID — VD-trace (s. asterisks in Fig. 2).
We begin our detailed discussion of the calibration functions considering gate voltages below threshold: For VG & lt- VT the barrier height parameter decreases linearly with the gate voltage,
Vo (Vg) = -^VG + v0, (7)
with p = 2/V and v0 = 2. To explain the linear relation in (7) we establish in the appendix the relation between the cSMA and the standard MIS capacitor model described in Refs. [16,17]. As a result, within the depletion approximation to the standard MIS capacitor model the linear dependence can be attributed to a constant body factor n of the
transistor which is defined in Eq. (12). It can be calculated from p according to
n = We • (8)
yielding the value n = 1.4 for our transistors. This result lies within the typical values for bulk MOSFETs ranging between 1.2 and 1.5 [14] and it is close to n = 1.6 found from the measured subthreshold slope (s. Fig. 5). Furthermore, one obtains from the standard MIS capacitor model the following:
Vbi + - Vfb = - vo, (9)
n q
i. e. v0 represents the material constants Vbi and VFB where Vbi is the built-in potential between the n±doped source contact and the p-substrate and VFB is the flat-band voltage of the MIS-structure [16].
From Fig. 3 © it can be taken that in the threshold- and subthreshold regime the overlap parameter takes the constant value of C = 0.1. In the appendix we argue that within the depletion approximation to the standard MIS capacitor model, the transverse confinement potential in the electron channel is given by the acceptor density in the substrate, essentially independent of the gate voltage (s. Eq. (15)). Since the confinement potentials in source- and drain contact are essentially independent of the gate voltage as well, the transversal overlap of the wave functions is seen to be approximately constant. One can show that within SMA it holds that 0 & lt- C & lt- 1, so that C = 0.1 indicates a rather poor wave-function-coupling between contacts and transistor channels caused by back-reflections.
Finally, in the threshold- and subthreshold regime the temperature calibration function in Fig. 3 (a) stays close to the room temperature value of u ~ 0.1. This is in agreement with the presence of only small tunneling drain currents in this regime leading to negligible Joule heating. To summarize, the results in Figs. 2 and 3 demonstrate that in the threshold- and subthreshold regime all ID — VD traces of the three transistors can be derived from only four constants, namely u = 0. 09, C = 0. 1, p = 2/V, and v0 = 2 ('-four-constants-fit'- in Figs. 2 and 3).
Above threshold voltage the chemical potential in the source contact rises above the maximum height of the barrier. Then the occupation of the lowest transverse level in the channel but also that of the higher transverse levels is strongly enhanced. This population of the electron channel leads to its widening as signaled by the increase in C. Furthermore, since the current grows due to the onset of classically allowed transport enhanced Joule heating occurs and the temperature increases rapidly. The widening of the electron channel and the heating of the transistor, in turn, favor the occupation of higher transverse channels in the electron channel and the SMA becomes invalid. As a consequence, the calibration parameters of the cSMA in Fig. 3 have to be regarded as pure fit-parameters in the ON-state. Therefore, at higher VG one has to consider as an artifact, first, the extent of the transistor heating and, second, the extent of the reentrant increase for the maximum barrier height above the chemical potential.
4. Conclusions
The combination of the recently developed SMA and a special fitting procedure with three calibration functions yields excellent quantitative agreement with experimental data. In the threshold regime and below, the calibration functions can be calculated from four constants only. Making contact to the standard MIS-model, these four constants
can be physically interpreted, allowing one calibration function to extract central device parameters: The body factor, the built-in potential between source and substrate, the flat band voltage and the wave function overlap factor between electron channel and contacts.
We gratefully acknowledge funding by the '-Nachwuchsforschergruppe Hybride Systeme des Landes Brandenburg'-.
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Quantitative Transport in Nano-transistors APPENDIX
A. Calibration functions in the standard MIS-model
+ qV. & gt-0
Ec (z)

m E
Fig. 4. Energy bands EC/V (z) of a standard MIS-structure (s. Fig. [2. 35] in [16]) and energy levels in the cSMA (times-italic font and filled left right arrows, s. Fig. 1) in one diagram. To arrive at the basic relation Eq. (10), first, EC (0) is set equal to the height of the potential barrier, v0EF in Eq. (3). Second, one identifies EC (Wd) = qVbi where Wd is the depletion layer width and qVbi is the built-in potential between source contact and p-substrate.
In the threshold- and subthreshold regime, it can be assumed that the quantum mechanical electron charge in the transistor channel is negligible against the charge of the ionized acceptors, which can be treated in standard device theory (s. Sect. 2 of [16]). In this depletion approximation the position of the bottom of the conduction band EC (z) in the standard MIS-model can be associated with the transverse quantum-confinement potential V (z) in the electron channel at zero drain voltage (s. Eq. (15)). For interpretation of the calibration functions in the cSMA we now plot in one diagram, shown in Fig. 4, the energy bands in the standard MIS-model (s. Fig. [2. 35] in [16]) and the energy levels in the cSMA (filled left right arrows in Fig. 1). To construct a plot of these quantities in the common energy diagram the energy zero is set to the bottom of the conduction band in the source. Furthermore, we equate the chemical potential in the source contact, ?j, = mEF, with the chemical potential in the bulk of the p-substrate because, both, the source contact and the back gate are grounded. It is assumed that the host material in the substrate and in the grounded source are the same. Then, the bottom of the conduction band in the bulk p-substrate EC (z & gt- Wd) is given by the built-in potential qVbi between the isolated host materials of the source contact and in the substrate. The barrier height v0 in Eq. (3) gives the position of the bottom of the conduction band EC (0) at the interface so that
voEf = Ec (0) = Ec (z & gt- Wd) — q^s = qVbi —
Fig. 5. Transfer characteristics of the experimental transistors in Fig. 3, dash-dotted lines for VD = 0. 1V and dashed lines for VD = 1. 0V. Open circles L = 22 nm, filled triangles L = 26 nm, and symbols '-+'- L = 30 nm. At the lower drain voltage, thermally activated behavior according to Eq. (14) is found with a slope [dlog101D/dVG]-1 — 96mV/decade, corresponding to n = 1.6 taken from the solid line. At the higher drain voltage thermal activation is overlayed with source-drain tunneling [11].
wheres is the potential drop across the space charge region of thickness Wd. Assuming a gate voltage controlled electron channel, one now writes in the standard MIS model the following:
VG — VFB = V + ^ = -Q + (11)
where VG is the applied gate voltage, V is the voltage that drops across the insulator barrier, Qs & lt- 0 is the total charge per area in the space charge region, and Ci is the constant insulator capacitance. In the depletion approximation the depletion layer capacitance can be written as CD = -8Qs/d^s = ts/Wd — ts/Wdm [s. Eq. (2. 201) of [16]]. Here, es is the dielectric constant of the p-substrate, and around the threshold, we may replace Wd by its maximum value Wdm so that CD is a constant. In this approximation Eq. (11) becomes = (VG — VFB)/n with a constant body factor
n =1 + CD. (12)
Insertion of this result in the basic relation (10) leads to the following:
V0 = -^VG + (Vbi + - VFB). (13)
nEF ef V n J
This equation has the same form as the numerical quantum-result (7). A comparison of (13) and (7) yields Eqs. (8) and (9).
In the assumed approximation Wd ~ Wdm one obtains from the standard model a constant inverse subthreshold slope [s. Eq. (3. 41) in [16]]
dlogwIn1 1
dV 2& quot-3-n, (14)
dVG q
which is found in the experimental transistors (s. Fig. 5) for small drain voltages. From the slope of the traces in their transfer characteristics one deduces S = 96mV/decade and then from (14) it follows that n = 1.6.
To finally discuss the overlap calibration function, one interprets EC (z) as the transverse confinement potential V (z) in the electron channel. In depletion approximation with Wd — Wdm it follows that
V (z) — 2^b (1 _ 777-^ + qVbi (15)
[s. Eqs. (2. 183) and (2. 187) of Ref. [16]]. Here = - where is the chemical potential of the intrinsic substrate semiconductor in the bulk. The channel confinement potential is seen to be essentially independent of the gate voltage. Therefore it is to be expected that the transversal overlap between the wave functions in the contacts and in the electron channel (and thus C) is independent of the gate voltage as well.

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